The Interlaken and Interlaken LA protocol is an interface standard of implementing a high-bandwidth and high-reliability transmission between chips. The protocol can establish a physical connection and a logical connection between chips based on the serial link technology. Because the protocol is applied to a large bandwidth range, and has expansibility and channel flexibility, at present, an interface applying the protocol has taken the place of the SPI-4.2 interface essentially, which makes the interface applying the protocol becomes the mainstream interface of a new generation of network processing chips and become the mainstream technology of high-speed connection in future.
With the fast increase of requirements of chips on data bandwidth and the fast increase of the number of meta-frame layer physical channels, new requirements for the reliability, compatibility and flexibility of a chip interface are made currently. By taking a chip which has an interface line speed exceeding 200G for example, the chip often needs about 24 physical channels of 10.3125G to implement the normal data transmission in practical application; but for some chips with large capacity, a few hundred physical channels will be needed in practical application; however, in the related technologies, the requirements of different applications are often met by integrating interfaces which can be compatible with multiple line speed bandwidths on one chip, which increases the complexity of the chip interface and brings a major challenge to the chip design while increasing the design cost and manufacture cost of the chip.
At present, the rate of the SerDes interface between chips becomes higher and higher, a big challenge is brought to the design of a single board and a backplane while a higher requirement for the reliability of the chip interface is made; specifically, in practical application, a chip interface often cannot work normally because of unstable working status of a SerDes interface of a certain link of the chip, or a wrong wiring connection or an unmatched connection order between an interface card and a line card in the design of a single board, which affects the application of the whole chip; besides, because of the rapid development of bandwidth requirement, a core router and a switch are frequently upgraded and updated, which makes a new requirement for the compatibility of the chip interface.